Current steering network

ABSTRACT

Sets of transistors each having a selectable number of emitters are employed for dividing current between the X and Y deflection means of an XY display device wherein each set of transistors defines a break point on a given alphanumeric character. Smooth transitions are made between each set of transistors and the next set, defining separate character break points, so as to generate a character stroke therebetween. Innumerable combinations of emitters are possible for generating different characters, each with a different group of transistor sets, and a large number of transistor sets for defining many characters are easily accommodated on a common integrated circuit structure.

United States Patent [19] Gilbert 11] 3,823,386 [451 July 9,1974

.[ CURRENT STEERING NETWORK [75] Inventor: Barrie Gilbert, Portland, Oreg. [73] Assignee: Tektronix, Inc., Beaverton, Oreg. 221 Filedr June 10, 1971 [21] Appl. No.: 151,927

Related US. Application Data [62] Division of Ser. No. 845,393, July 28, 1969, Pat. No.

Y OUTPUT Bryden 340/324 A Primary Examiner-Harold l. Pitts Attorney, Agent, or Firm-Klarquist, Sparkman, Campbell, Leigh, Hall & Whinston [57] ABSTRACT Sets of transistors each having a selectable number of emitters are employed for dividing current between the X and Y deflection means of an XY display device wherein each set of transistors defines a break point on a given alphanumeric character. Smooth transitions are made between each set of transistors and the next set, defining separate character break points, so as to generate a character stroke therebetween. lnnumerable combinations of emitters are possible for generating different characters, each with a different group of transistor sets, and a large number of transistor sets for defining many characters are easily accommodated on a common integrated circuit structure.

6 Claims, 12 Drawing Figures X OUTPUT PATENTEDJUL 91914 3.823.386

SHE! 2 OF 5 FIG. 4

FRACTION OF I: INTO X OUTPUT CURRENT STEERING NETWORK CROSS-REFERENCE TO RELATED APPLICATION This application is a division of my application Ser. No. 845,393, filed July 28, 1969, now U.S. Pat. No. 3,651,510.

BACKGROUND OF THE INVENTION Several schemes are available for generating alphanumeric characters for display on an XY display device such as an oscilloscope. Characters may be formed, for example, through the generation of a large number of dot elements in a dot raster or the like with some of the dots being selected for display in response to a given character command. The circuitry involved with this approach is fairly complicated, and the time for the generation of an individual character may be longer than desired. Also, of course, the presentation is discontinuous. A secondapproach involves the generation of segments or strokes having the nature of vectors defined by a given starting point and a given direction. Al-

though a character is then made up of fewer, elements, the number of available vectors is frequently limited, resulting in the generation of characters which are rather unlike the desired printed appearance of alphanumeric characters. In my copending application, Ser.

SU MMARY OF'THE INVENTION In accordance with the present invention, a character is generated employinga plurality of sets of transistors wherein a first transistor in each set is adapted to. provide an output current for causing X deflection in an XY display device, and wherein a secondtransistor in each set is adapted to provide an output. current for causing Y deflection in the display device. The first and second transistors deliver the different output currents by virtue ofdifferingtotal emitter areas. Preferably this difference in emitter areas is established by connecting a different number of emitters in the case of each such transistor. Means are provided for smoothly scanning between sets of transistors so that XY deflection of the XY display device will smoothly change from one set of coordinates to a next setof coordinates thereby generating a segment between break points of a character.

A large number of area ratios of transistor emitters are available for defining a large number of different break points and segments therebetween. Therefore different sets of transistors assembled into different groups may be connected to generate substantially any desired selection of characters. The transistors are greatly miniaturized in the semiconductor integrated circuit embodiment of the present invention whereby ten characters,

for example; may be accommodated on one semiconductor chip. The scanning means employed for operating the transistor sets is also suitably accommodated on the same chip. 7

In accordance with one embodiment of the present invention, the scanning means comprisesa ladder network driven by complementary current ramps and adapted to smoothly scan the transistor sets. The ladder network may comprise resistors, or in another embodiment, the ladder network may comprise a plurality of reverse-connected diodes connected in series defining nodes therebetween and a further plurality of diodes connecting the nodes to a common reference point, while current sources drive the aforementioned nodes. In the case of either ladder network embodiment, the node points drive control elements, e. g., transistors, for steering a current.

It is accordingly an object of the present invention to provide an improved character generator apparatus capable of extreme miniaturization.

It is a further object of the present invention to provide an improved character generator apparatus for operating an XY display device, such generator developing character strokes segments wherein a large number of strokesor segments are selectable.

It is another object of the present invention to provide an improved character generator apparatus having an unrestricted scanning speed.

It is a further object of the present invention to provide an improved character generator apparatus wherein the characters can be electrically sizefollowing description taken in connection with the accompanying drawings wherein like reference characters refer. to like elements.

DRAWINGS FIG. 1 is a schematic diagram of a circuit employed according to the present invention;

FIG. 2 is a schematic diagram of a preferred circuit employed according to the present invention;

FIG. 3 is a simplified diagram for illustrating the principles of the character generator apparatus according to the present invention;

FIG. 4 is a schematic diagram of a first scanning circuit according to the present invention together with input and output waveforms therefor;

FIG. 5 is a voltage profile for the FIG. 4 scanning circuit;

FIG. 6 is a schematic and block diagram of a preferred character generator circuit according to the present invention;

FIG. 7. is a display of a character generated by the FIG. 6 circuit;

FIG. 8 illustrates a matrix for employing a plurality of circuits of the FIG. 6 type in a character generator apparatus; 1

FIG. 9 is a magnified plan view of a portion of a semiconductor integrated circuit embodiment of the character generator according to the present invention;

FIG. 10 is a partial cross section taken at 10-10 in FIG. 9;

FIG. 1 l is a schematic diagram of an alternative scanning network according to the present invention; and- FIG. 12 is a chart of waveforms illustrative of operation of the FIG. 11 circuit.

DETAILED DESCRIPTION In FIG. 1, illustrating a circuit employed according to the present invention, a first NPN transistor 10 includes a base 12, a collector 14, and an emitter 16. A second NPN transistor 18 comprises a base 20, a collector 22, and an emitter 24, while a third NPN transistor 26 similarly includes a base 28, a collector 30, and an emitter 32. Bases 12, 20, and 28 are grounded while the emitters are connected together at terminal 34 through which a total current I flows. The transistors divide the current I into three currents, I l and I The three emitters 16, 24, and 32 have areas which are, in general, unequal. It is easily shown that the output currents I and Iy are IX: AX/AX Ay AZ and I Ay/A Ay I AZ where A Ay and A are the areas of the emitters. I

is not employed directly but represents the residue, [,3

I Iy. The value of I determines the proportion of I that is then divided between I and Iy. The division ratios are independent of temperature or the current I especially when the transistors are formed as part of a common semiconductor circuit structure. As hereinafter indicated,the currents I and I) are suitably employed to bring about deflection in orthogonal directions of an electron beam or the like in an XY display device such as an oscilloscope. The presentation defined by a particular I and a particular Iy defines a break point of a character or symbol displayed. Thus the respective emitter areas of the three transistors define the exact location of the particular point or break point.

A more convenient realization of variable area emitters is illustrated in FIG. 2 wherein transistors 10', I8, and 26' correspond to similarly numbered transistors of FIG. 1. Each ofthe FIG. 2 transistors is provided with multiple emitters, only some of which are connected. The number of emitters of transistor 10' equals N while the number of transistor 18' emitters which are connected equals N and the number of transistor 26' emitters which are connected equals N If each elemental emitter has the same area, the outputs are now The multiple emitters are preferable from the standpoint of reproducibility of desired area ratios and the ease in which the circuit is realized in an integrated circuit structure. For example, each of the transistors is formed with five (or more)'emitters, and only some of the emitters are connected in the course of manufacture to provide a current ratio desired. A plurality of such sets or trios of transistors are suitably formed on the same integrated circuit chip with only the selection of the number of emitters connected varying from one set or trio to the next.

FIG. 3 illustrates eight sets or trios of transistors, each having a multiple number of emitters connected, and which are selectively energized in accordance with the waveforms at the left-hand side of FIG. 3. Thus, a first set of transistors comprising transistors 36, 38, and 40 are driven in common at base electrodes connected to terminal 42 with a positive square wave 44. Immediately at the conclusion of positive square wave 44, a positive square wave 46 is applied to terminal 48 connected to the bases of a set of transistors 50, 52, and 54. Then, a positive square wave 56 is immediately applied to terminal 58 driving the bases of transistors 60, 62, and 64. Subsequent square waves 66 through 70 are applied in sequence to terminals 71 through 75 driving further sets or trios of transistors. One collector of a transistor of each trio is connected to X output terminal 76, while a second collector terminal of a transistor of each trio is connected to a Y output terminal 78. These output terminals are connected to provide horizontal and vertical deflection in an XY display device 79, the latter suitably comprising a cathode ray oscilloscope. The remaining transistor of each trio or set is grounded to dump a residue output current. All of the connected emitters of the various transistors are coupled in common to terminal through which a tail current I flows.

As can be seen in FIG. 3, one emitter of transistor 36 is connected to terminal 80, none of the emitters of transistor 38 are connected to terminal 80, and three emitters of transistor 40 are connected to terminal 80. Each of the elemental emitters are equal in area, and therefore the current applied to the top set of transistors will be divided into four parts, during time period I, when waveform 44 is applied at terminal 42. Onefourth of the current I will be provided as an X output at terminal 76, none of the current I will be provided at terminal 78, and the remainder will be grounded through transistor 40. Then, when the transistor set 50, 52, 54 is energized by waveform 46 applied to terminal 48, two-fifths of the current I is delivered to X output terminal 76 inasmuch as two emitters of transistor 50 are connected out of a total of five connected emitters in the set. Similarly, one-fifth of the current will be delivered at Y output terminal 78, and the remainder of the current flows to ground. When waveform 56 is applied at terminal 58, half of the current I,,- is delivered to the X output terminal 76 and onethird is delivered to the Y output terminal 78. It is seen that as the trios of transistors are sequentially operated by the waveforms indicated at the left-hand side of FIG. 3, the X output and Y output waveforms indicated at the righthandside of FIG. 3 will be produced at times t, through i The FIG. 3 outputs are by way of example only, and do not represent any particular character. As a matter of fact, employing the X output and the Y output indicated in FIG. 3, a number of points or dots will be presented on an XY display device.

From FIG. 3 it can be observed that the number of emitters of an energized transistor connected to the X output and. the number of emitters of a transistor connected to the Y output will determine the ratio of currents delivered as between the X and Y outputs. But if the total of the X and Y currents always equal I the result is a limited number of locations for display points thereby defined. With the use of the third column of transistors, the collectors of which are grounded, adjustment in the particular values of the X and Y output currents is permitted since the total of the X and Y output currents is thereby determined. A number of possible deflection points for an XY display apparatus driven by eight trios of transistors is indicated by the array ofdots illustrated in FIG. 7. The transistor trios employed to provide this range of points is further illustrated in FIG. 6 and described in connection therewith.

As mentioned above in connection with FIG. 3, the sequencing control of the respective transistor sets or trios employing square waveforms results in a series of dots, only, on an XY display device, which would require a large number of transistor sets in order to form a complete character. Each time a positive square wave is applied to the base electrodes of a set of transistors, the XY display jumps from one point to the next. A preferred arrangement according to the present invention is illustrated in FIG. 4 for smoothly and gradually sequencing between sets of transistors. Referring to FIG. 4, transistors 81 through 88 represent the sets of transistorsas hereinbefore described, and means comprising a ladder network is employed in. conjunction with these transistors for smoothly transferring a current, I,;, between the transistors, such current I being connected in common to the transistor emitters. A pair of complementary smoothly changing current ramp waveforms 90 and 92 are applied between input terminals 94 and 96, these waveforms comprising portions of triangular waves. Between times t and t, the current ramp waveform 90 increases linearly from zero to a negative maximum value I At the same time, the current waveform 92 decreases froml to zero. The ladder minals 94 and 96, i.e., as when current ramps 90 and 92 are each in mid-swing, the voltage distribution at the aforementioned network nodes is as appears in FIG. 5.

curve to have a flat-topped. indistinct maximum. Similarly, if resistors 98 were too small in value, the potential would be almost the same at every node and a much flatter overall curve would result- Typical resistance values are hereinafter indicated in connection with the embodiment of FIG. 6. In general, resistors 100 are large in value as compared with resistors 98.

As will be seen, transistors 84' and 85 receive the most positive voltage for the inputs defined by the curve in FIG. 5 and at this timetransistors 84 and 85 will equally share the current I As the ramp waveforms and 92 are complementarily changed in value, the FIG. 5 waveform will become asymmetrical with the maximum successively appearing at the different nodes thereby selecting transistors 81 through 88 in sequence. The tail current I will gradually shift between the transistors providing the smoothly changing outputs indicated at the right-hand side of FIG. 4. If now, instead of transistors 81 through 88, the trios of transistors of FIG. 3 are substituted, it will be seen that the X and Y outputs smoothly change between current values rather than immediately jumping from one value to the next. Consequently, a resultant display in an XY display device will smoothly execute strokes of a character between the points or break points defined by the transistor trio current divisions, as the current smoothly shifts from one trio to the next. A combined circuit suitable for integrated circuit realization is illustrated in FIG. 6. I

Referring to FIG. 6, sets or trios of transistors 101 through 108 have certain connected emitters thereof returned to a common emitter bonding pad 110 of a semiconductor integrated circuit structure. The collectors of the left-hand transistors of these sets are connected in common to X output bonding pad 114 while the collectors of the middle transistors of each set are connected to Y output bonding pad 112. The collectors of the remaining or residue'curren't transistors are con nected to +5 volt terminal 116.

A ladder network comprising series resistors 98 and shunt resistors 100 is employed in FIG. 6 fordriving the transistor sets 101 through 108, this ladder network being of the type illustrated in FIG. 4. A triangular voltage waveform is suitably applied at pad 118 connected to the base of transistor 120 which forms half of a differential pair with transistor 122. The emitter of transistor 122 is connected to bonding pad 124 through resistor 126, and a resistor 128 couples the emitters of transistors 120 and 122. A series circuit comprising resistor 127 and Zener diode 129 is disposed between a +5 volts and bonding pad 124, with the base of transistor 122 connected to the midpoint of this circuit. A source of voltage is connected to bonding pad 124 so that as the triangular waveform is applied at pad 118, complementary triangular waveforms of current are supplied at terminals 94 and 96 of the ladder network as was illustrated with respect-to FIG. 4. Pad 124 connects to the device substrate. Bonding pad 130 is employed to select the integrated circuitry package" illustrated in FIG. 6 and is coupled via resistor 132 to the base of transistor 134, the emitter of which is coupled to +5 volts through resistor 136. The collector of transistor 134 is connected to the baseof transistor 138. The emitter of transistor 138 is connected to common ladder terminal 140 and the collector of transistor 138 is returned to +5 volts.

' With pad 130 disconnected or connected to a relatively positive voltage, no current flows in transistors 134 and 138, leaving network terminal 140 at a low value. Zener diodes 148 and 150 are employed to .catch" terminals 94 and 96 at approximately l.5

volts, so that these points will not become any more negative than this value, e.g., when terminal 140 is not positively energized. However, when pad 130 is grounded, both transistors 134 and 138 conduct and terminal 140 is coupled through transistor 138 to a volts. As a result, one of the voltages V through V at the nodes of the network will then be positive enough to energize one of the transistor sets 101 through 108, and if current is applied at pad 110, then current division thereof as between output terminals 112 and 114 will be dictated according to the number of emitters connected within the transistor set which is selected by the resistive ladder network. Pad 130 is suitably energized or de-energized according to a selection matrix as hereinafter described in connection with FIG. 8.

Let us assume that the voltage V is maximum, at some point during the triangular waveform applied at pad 118. Then the transistor set 107 will have a more positive voltage applied to the base electrodes of its trio of transistors than will be the case for the other transistor sets. As a consequence, current delivered at pad 110 will be divided in accordance with the connected emitters of set 107. In this trio, as in each of the others 7 in the same column, the right-hand transistor, 146, is

' provided with eight emitters, while the middle and leftpad 110 will flow in transistors 142 and l44jointly, and

half of that current will flow in transistor 146. Thus, one-fourth of the total current available will be provided at that time to X output terminal 114.

The column of transistor sets 101 through 108 have emitters connected for providing a representation of the FIG. 9" on an XY display device. This representation is illustrated in FIG. 7, wherein each of the break points 151 through 158 correspond to the point selected by the transistor sets 101 through 108respectively. Of course, break points 154 and 158 coincide to complete a closed figure. It is noted that since the current smoothly changes from one transistor set to the next, the representation of the numeral 9 in FIG. 7 comprises a series of segments between the break points 151 through 158, and not just the break points themselves. Thus, the X and Y currents provided to oscilloscope deflection apparatus or the like smoothly change from one value to another, and the electron beam or the like of such XY display apparatus smoothly moves between the break points. This charac-' ter may later be compressed in a horizontal direction by deflection circuit means (not shown).

The remaining dots illustrated in FIG. 7 represent the possible combinations of emitters which may be connected for a trio of transistors having five possible X and Y" emitter connections and eight possible Z emitter connections. Thus, a wide variety of possiblilities are presented for the formation of various symbols and characters. It is always desired that the actual connected emitters in a set total between eightand in this particular embodiment to avoid some portions of a character being brighter than others. While other break points are possible besides those illustrated in FIG. 7, this field of points will define most characters trio 107 hereinbefore discussed wherein the X and Y currents provided by transistors 142 and 144 are equal, while the total thereof was just half the total possible current corresponding to the dot in the upper righthand corner of FIG. 7.

Other columns of transistors 160 through 168 are suitably accommodated upon the same die with each such column representing a particular alphanumeric character. Each column is like the one comprising sets 101 through 108 except the emitter connections are different. The various characters are respectively selected by providing current to one of the pads 170 through 178 respectively instead of pad 110 whereby one of the other columns is selected. It will be understood that otherwise each of the columns is suitably connected to the rest of the circuitry substantially identically to the column comprising transistor sets 101 through 108, with these sets being energized by the same ladder network by voltages V, through V in sequence. In the FIG. 6 configuration, the resistor scanning network comprising resistors 98 and 100 is desirably located in the middle of the die with five columns of transistors located on either side thereof in symmetrical fashion. The symmetrical arrangement minimizes the length of metalization paths and voltage drop which may occur therealong in the integrated circuit realization. The outputs of the columns 160 through 168 are also respectively connected to the X and Y output terminals as well as to the +5 volt terminal for the residue current from the right hand transistors of each such column.

As illustrated in FIG. 6, the scanning network comprising resistors 98 and 100 is desirably formed with the resistors having resistance values which taper, becoming larger toward the center of the ladder in order to produce a nearly constant scanning rate along the entire character to be presented. Without the linearizof interest. The coordinate axes indicate relative or v proportional'values of the X and Y currents. For example, it is noted that point 157 in FIG. 7 corresponds to ing effect of this tapering, some parts of the character are apt to be scanned more rapidly and will be dimmer than other parts.

Among the advantages of the scanning system according to the present invention is that a substantially unlimited number of strokes are readily provided by means of transistor integrated circuit structure and this structure consumes a very small space in an oscilloscope or the like. There is also no restriction on scanning speed, but the characters can be generated from very slow speeds to well over a million a second. Also, the characters are size-controlled by a signal allowing rapid electronic switching between two or more display sizes if desired. For example, the value of the current applied to pad or one of the pads through 178 determines the size of the character. As will also be seen from FIG. 8, a number of the structures of the FIG. 6 type areeasily matrixed together in order to provide a larger number of characters.

Referring to FIG. 8, a selection matrix is illustrated wherein blocks 180, 182, and 184 indicate integrated circuit structures or dies of the type illustrated in FIG. 6, and will each be designated as a row. The column select lines in FIG. 8 connect to the column current pads such as pads 110 and 170 through 178 in FIG. 6. Thus, as illustrated in FIG. 8, corresponding columns for the different structures are connected together. The row selector terminals 186, 188, and correspond to the bonding pads 130 in each structure. Also, the X output and the Y output of the different structures are 9 coupled via amplifiers 192and 194 to the X and Y deflection means respectively in the cathode ray tube 196. By energizing one of the column-select lines, and one of the row selector terminals, a particular character for display is designated, and then a triangular scanning wave applied to terminal 118' (corresponding to the similarly numbered terminal in FIG. 6) causes execution of such character. After a suitable number of scans or cycles of a triangular scanning wave applied at terminal 118, switching circuitry (not shown) 'may change the selection to different characters by energizing different column and row lines and terminals.

In FIG. 9, comprising a magnified plan view of an integrated circuit construction in accordance with the FIG. 6 diagram, the extreme miniaturization possible accordingto the present invention can be visualized. The broken away portion illustrated in FIG. 9 is approximately l8 mils by l8.mils. Referring to FIG. 9, and to FIG. 10 taken at 1010 in FIG. 9, a substrate 198, suitably formed of P type semiconductor material, is superimposed by an N type epitaxial layer 200 divided off by isloation diffusion 202 which is P type. A conventional N+buried layer (not shown) is also incorporated between the substrate and region 200. P type base diffusions 204 are provided between N type emitter diffusions 206 and epitaxial layer 200. Conductors 208, 210, 212, 214, and 216 are disposedover the emitter diffusions and make contact with selected of these emitter diffusions through apertures 296 in an oxide layer 204. The conductors 208 through'216 can make contact with selected of the emitters in accordance .with masks employed for removing such oxide layer at locationswhere it is desired to make contact with an emitter. Except for such a selective mask, the process of forming the semiconductor structure is the same, no matter what characters or symbols are to be generated thereby. Appropriate connection is made in a similar manner from the base diffusions to conductors 290, and from the epitaxial region to conductors 292 via N+ emitter diffusions such as 300. Conductors 292 provide collector contacts. It is noted multiple base connections 290 are employed to make sure the base potentials are everywhere the same as within a transistor trio. Emitters are always adjacent a base contact.

The conductors 208 through 216 in FIG. 9 correspond to the column conductors connected to bonding pads 110, and 170 through 173 in FIG. 6. Thus, FIG. 9 illustrates the lower left-hand portion of the FIG. 6 circuitry comprising all five columns up as far as the third trio of transistors in each column. Epitaxial region 218 corresponds to a common collector connected to an X output bonding pad via a conductor 292, while re gion 220 comprises the epitaxial collector region connected to a Y output bonding pad. Similarly, region 222 corresponds to the right-hand transistors for each of five rows wherein the epitaxial collector region is connected to a +5 volt terminal.

Since the circuit employs common collector connections over a great number of transistors, the entire FIG. 6 circuit, so far as the trios of transistor sets are concerned, is divided into only six collector regions as defined within isolation difiusions such as illustrated at 202. As a consequence of these few common collectors, the considerable miniaturization is made possible.

FIG. 11 illustrates a second scanning network in accordance with the present invention which may be employed in place of the network comprising resistors 98 and 100 as illustrated in FIGS. 4 .and 6. In place of series resistances, this network employs reverseconnected diodes 224-226, 228-230, and 232-234 disposed in series between terminals 244 and 246. The reverse-connected diodes separate nodes 272, 274, 276, and 278. Terminals 2A4 and 246 are suitably driven by complementary ramp currents (such as waveforms and 92 respectively, in FIG. 4) as may comprise portions of a triangular wave. Current sources 236, 238, 240, and 242 each provide a unit current, I, to nodes 272, 274, 276, and 278, respectively. Also connected to these nodes are anode terminals of diodeconnected transistors 248, 250, 252, and 254, the cathodes? of which are returned to ground at point 256. In addition the nodes drive transistors 258, 260, 262, and 264, the common emitter current, I,.;, of which flows through terminal 266. Transistors 258, 260, 262, and 264 provide output currents I,, I,, I,, and I and each of these transistors represents a trio of transistors as hereinbefore described.

The circuit of FIG. 11 has the advantage that the output currents I, through I at the outputs of the transistors change substantially linearly as ramp current waveforms are provided at terminals 244 and 246. The linear output obtained is depicted in the FIG. 12 waveform chart. In the case where transistors 258 through 264 represent the transistor trios as hereinbefore described, the linear current changes causes a constant 'changein deflection in an XY display device, that is, a substantially constant deflection velocity between character break points represented by the transistors. As a result, character strokes will have more nearly the same intensity therealong.

Considering operation of the FIG. 11 circuit, the re verse-connected diodes 224-226, 228-230, and 232-234 tend to conduct little current unitil a predetermined voltage occurs thereacross. Thereafter, current may increase, but the voltage drop remains nearly constant. Let us assume were discussing a four stage circuit and that at a particular instant current ramps are provided at terminals 244 and 246 such that three units of current, or 3I, flows through terminal 246 and zero units of current flow through terminal 244. Then, these three units flowing through terminal 246 must come from current sources 238, 240, and 242. The remaining unit current from source 236 must flow through diodeconnected transistor 248 producing a voltage drop thereacross for energizing transistor 258. None of the other diode-connected transistors 250, 252, or 254 receive current, but rather the current from sources 238 and flows through diodes 228-230 and 232-234. Now'assume the ramp waveforms applied at terminal 244 and 246 are such that two units of current, or 2I, flows through terminal 246, and one unit, I, of current flows through terminal 244. The one unit of current through terminal 244 comes from source 236. The two units of current flowing through terminal 246 comes from sources 240 and 242. The remaining unit current from sources 238 flows through diode-connected tran sistor 250 providing a voltage drop operating transistor 260. In like manner, as the ramp currents applied to terminals 244 and 246 change, the remaining transistors 262 and 264 are successively operated. The transistion of current I between transistors 258, 260, 262, and 264 is smooth as in the previously described ladder network. Furthermore, substantially linear outputs are 1 1 provided. The diode-connected transistors linearize the operation of transistors 258264. Ordinary diodes may be employed, but a good characteristic match with respect to transistors 258264 is desired and therefore diode-connected transistors on the same integrated circuit structure as transistors 258264 are preferred.

It is noted that the total of currents flowing through terminals 244 and 246 is not equal to the sum of the unit currents from sources 236, 238, 240, and 242. Rather, one additional unit current is provided by the last mentioned sources which then flows through one of the diode-connected transistors 248 through 254, or two of the diode-connected transistors during transitions. The circuit is alternatively operable for switching or commutating the currents I without transistors 248 through 254, in which case the sum of the currents at terminals 244 and 246 equal the sum of the currents from the current sources. Such a circuit is useful for analog to digital conversion, with the transitions being more abrupt, rather than changing in a linear manner as depicted in FIG. 12.

in most practical cases, the current sources 236 through 242 will comprise fairly large resistors having the terminals thereof, remote from node points 272 through 278, connected to a common reference point. Although diodes are preferred at locations 224-226, etc., to minimize drive requirements, resistors may alternatively be employed at these locations if desired. It is also noted that although the ladder circuits of FIG. 11 and FIG. 4 are eminently suitable for operating the transistor sets comprising the present character genera tor, these ladder networks can also be employed for commutating or steering currents for other purposes.

While I have shown and described preferred embodiments of my invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from my invention in its broader aspects.

I claim:

1. A steering network comprising:

first and second terminals,

a plurality of impedance means in series between said first and second terminals defining node points therebetween,

a plurality of parallel circuit means coupled to said node points,

voltage responsive devices coupled to respective node points for selective energization therefrom,

and coupling means for applying complementary smoothly changing currents between said pair of terminals of said network to provide voltages at said node points for sequentially operating said voltage responsive devices in order.

2. The network according to claim 1 wherein said series impedance means and said parallel circuit means comprise resistors.

3. The network according to claim 1 wherein said series impedance means comprise pairs of reverseconnected diodes and wherein said parallel circuit means comprise current sources.

4. The network according to claim 3 wherein said current sources comprise resistors.

5. The network according to claim 3 further including a plurality of diode means coupling said nodes to a third terminal, selected ones of said diode means coupling current from a said current source to said third terminal according to the complementary currents applied to said first and second terminals.

6. The network according to claim 5 wherein said diode means comprise diode-connected transistors and wherein said voltage responsive means comprise tran- UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,823,386 at d July 9, 1974 Inventor(s) Barrie Gilbert It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 3, line I 30, "I =A /A -l -A +A I should be Column 3, line 31, "I =A /A +A +A I should be P R A I o I =i T-,- VK +"A T Z E Column 3, line 60, "I '=N /N +N +N I should be s X v I '=W FN I n X X Y z E Column 3, line 61, "I =N /N =N +N IE" should be I I C Column 10, line 29 "causes" should be --cause-- Signed and sealed this 3rd day of December 1974.

(SEAL) 'At st= n McCOY GIBSON JR. C. MnRsl lALh. DANN A Attesting Officer commlsslonet' of Patents FORM Po-1o50 (10-69) USCOMM-DC 603764 69 U45. GOVERNMENT PRINTING DFFICE 1!! 03G-83l 

1. A steering network comprising: first and second terminals, a plurality of impedance means in series between said first and second terminals defining node points therebetween, a plurality of parallel circuit means coupled to said node points, voltage responsive devices coupled to respective node points for selective energization therefrom, and coupling means for applying complementary smoothly changing currents between said pair of terminals of said network to provide voltages at said node points for sequentially operating said voltage responsive devices in order.
 2. The network according to claim 1 wherein said series impedance means and said parallel circuit means comprise resistors.
 3. The network according to claim 1 wherein said series impedance means comprise pairs of reverse-connected diodes and wherein said parallel circuit means comprise current sources.
 4. The network according to claim 3 wherein said current sources comprise resistors.
 5. The network according to claim 3 further including a plurality of diode means coupling said nodes to a third terminal, selected ones of said diode means coupling current from a said current source to said third terminal according to the complementary currents applied to said first and second terminals.
 6. The network according to claim 5 wherein said diode means comprise diode-connected transistors and wherein said voltage responsive means comprise transistors. 